The field of invention relates to electrical circuitry in general; and, more specifically, to memory controller circuits.
Memory controller circuits can be used in a variety of computer systems (e.g., desktop personal computers, notebook computers, personal digital assistants, etc.) to facilitate the computer system""s processor in accessing memory chips. These memory chips may include random access memory (RAM) chips. For example, a memory controller can have an interface for connecting to one or more dynamic RAM (DRAM) chips such as, for example, synchronous DRAM (SDRAM) chips. The memory controller uses this memory interface to route data between the processor and RAM chips and to send address and control signals to the RAM chips. The control signals for accessing a RAM chip typically include row address strobe (RAS), column address strobe (CAS), write enable (WE) and chip select (CS) signals.
As in other electrical interfaces, the memory interface of a memory controller dissipates power during transitions (also referred to herein as toggling) of the interface signals. For example, in conventional memory controllers, during each memory cycle, the memory interface will drive the address and control signals at the beginning of the cycle and then return the signals to an idle state near the end of the cycle. For control signals, the idle state may be a logic high level, while for address signals, the idle state may a logic low level. Nevertheless, whatever the logic level of the idle state, returning these signals to the idle state generally causes toggling of many of these signals. As previously described, toggling results in power dissipation, which is generally undesirable in computer system applications and especially in battery-powered computer systems such as notebook computers and personal digital assistants. In addition, simultaneous toggling of such signals can result in increased noise and peak power dissipation. This problem can be further exacerbated in controllers for use with multiple system buses.